In this paper an ultra-low power two stage improved Operational trans_conductance Amplifier based on folded cascode is designed. The proposed Operational trans_conductance Amplifier operates in weak inversion region. The use of two folded branches in the signal amplification path for the first stage and the new feed_forward compensation path with low bias current on the second stage in this proposed Amplifier increases the DC gain, unity gain frequency, slew rate and decreases the input referred noise. The simulation results in a TSMC 0. 18μ m CMOS technology it shows that the proposed Operational trans_conductance Amplifier has unity gain bandwidth of 117 KHz, and consumes 195 nW power from a 0. 6 V supply voltage with DC gain of 101. 4 dB.

In this paper the analysis and design of an Operational Amplifier is presented. This Amplifier can follow the input signal from ground to supply voltage at its input and output. Based on the level of the input common mode voltage, one of two pMOS and nMOS differential pairs are selected to amplify the input signal. This causes the Amplifier performance is independent of the drain current relationship of the input differential pairs transistors. Both static and dynamic currents of the class AB output stage are provided by two translinear loops with minimum sensitivity to process, temperature and supply voltage variations. The simulation results, in a 0.18  CMOS technology, show that the Amplifier in nominal condition, has about 80 dB dc voltage gain, 51 MHz unity gain bandwidth and 63  phase margin while its static power consumption is almost 1 mW. For input common mode voltage changes between ground to the supply voltage, the maximum relative variations of the input differential pairs transconductances, Amplifier’s dc voltage gain, phase margin and unity gain bandwidth are , ,  and , respectively. This Amplifier as a buffer can drive a load consisting of parallel connection of a resistor  and a capacitor 20 pF.

In this paper, we propose an efficient approach to design optimization of analog circuits that is based on the reinforcement learning method. In this work, Multi-Objective Learning Automata (MOLA) is used to design a two-stage CMOS Operational Amplifier (op-amp) in 0. 25μ m technology. The aim is optimizing power consumption and area so as to achieve minimum Total Optimality Index (TOI), as a new and comprehensive proposed criterion, and also meet different design specifications such as DC gain, Gain-Band Width product (GBW), Phase Margin (PM), Slew Rate (SR), Common Mode Rejection Ratio (CMRR), Power Supply Rejection Ratio (PSRR), etc. The proposed MOLA contains several automata and each automaton is responsible for searching one dimension. The workability of the proposed approach is evaluated in comparison with the most well-known category of intelligent meta-heuristic Multi-Objective Optimization (MOO) methods such as Particle Swarm Optimization (PSO), Inclined Planes system Optimization (IPO), Gray Wolf Optimization (GWO) and Non-dominated Sorting Genetic Algorithm II (NSGA-II). The performance of the proposed MOLA is demonstrated in finding optimal Pareto fronts with two criteria Overall Non-dominated Vector Generation (ONVG) and Spacing (SP). In simulations, for the desired application, it has been shown through Computer-Aided Design (CAD) tool that MOLA-based solutions produce better results.

In this paper, a new two-stage OTA is proposed which meeting the needs of high gain, low power and low noise, and designed based on the gm/ID technique with bulk driven method. It is noteworthy that due to the limitations of CMOS technology, CNTFET technology used for the circuit designs. Moreover, to improve the linearity of the circuit, triode transistors used in both stages of Amplifiers. The simulation results of the proposed OTA are performed under 1V of supply voltage and 1pF of load capacitors in the HSPICE tool. According to the simulation results, the proposed circuit consumes less than 27 μ W of power and offers a high gain of 98 dB. The CMRR and PSRR values of the proposed circuit are 121 dB and 152 dB, respectively. The input referred noise is 0. 92 nV/√ Hz and the slew rate of the proposed circuit is 111 V/μ s, which shown the better figure of merit (FOM) in compression with the previous works.

The Operational transconductance Amplifier-capacitor (OTA-C) filter is one of the best structures for implementing continuous-time filters. It is particularly important to design a universal OTA-C filter capable of generating the desired filter response via a single structure, thus reducing the filter circuit power consumption as well as noise and the occupied space on the electronic chip. In this study, an inverter-based universal OTA-C filter with very low power consumption and acceptable noise was designed with applications in bioelectric and biomedical equipment for recording biomedical signals. The very low power consumption of the proposed filter was achieved through introducing bias in subthreshold MOSFET transistors. The proposed filter is also capable of simultaneously receiving favorable low-, band-, and high-pass filter responses. The performance of the proposed filter was simulated and analyzed via HSPICE software (level 49) and 180 nm complementary metal-oxide-semiconductor technology. The rate of power consumption and noise obtained from simulations are 7.1 nW and 10.18 nA, respectively, so this filter has reduced noise as well as power consumption. The proposed universal OTA-C filter was designed based on the minimum number of transconductance blocks and an inverter circuit by three transconductance blocks (OTA).

In this work, a low power, low voltage and high gain Operational Amplifier is proposed. For this purpose, a negative resistance structure is used in parallel with output to improve the achievable gain. Because of using self cascode transistors in the output, the proposed structure remains approximately constant in a relatively large output voltage swing causing an invariable gain. To evaluate the proposed method an op amp was designed in 0.18mm CMOS technology. The simulation results showed a gain of 84dB, unity gain bandwidth of 12.45MHz and phase margin of 81 degree, with 1V power supply and 1pF load capacitor.

Background and Objectives: In recent years, the electronics industry has experienced rapid expansion, leading to increased concerns surrounding the expenses associated with designing and sizing integrated circuits. The reliability of these circuits has emerged as a critical factor influencing the success of production. Consequently, the necessity for optimization algorithms to enhance circuit yield has become increasingly important. This article introduces an enhanced approach for optimizing analog circuits through the utilization of a Multi-Objective Evolutionary Algorithm based on Decomposition (MOEA/D) and includes a thorough evaluation. The main goal of this methodology is to improve both the speed and precision of yield calculations.Methods: The proposed approach includes generating initial designs with desired characteristics in the critical analysis phase. Following this, designs that exceed a predefined yield threshold are replaced with the initial population that has lower yield values, generated using the classical MOEA/D algorithm. This replacement process results in notable improvements in yield efficiency and computational speed compared to alternative Monte Carlo-based methods.Results: To validate the effectiveness of the presented approach, some circuit simulations were conducted on a two-stage class-AB Op-Amp in 180 nm CMOS technology. With a high yield value of 99.72%, the approach demonstrates its ability to provide a high-speed and high-accuracy computational solution using only one evolutionary algorithm. Additionally, the observation that modifying the initial population can improve the convergence speed and yield value further enhances the efficiency of the technique. These findings, backed by the simulation results, validate the efficiency and effectiveness of the proposed approach in optimizing the performance of the Op-Amp circuit.Conclusion: This paper presents an enhanced approach for analog circuit optimization using MOEA/D. By incorporating critical analysis, it generates initial designs with desired characteristics, improving yield calculation efficiency. Designs exceeding a preset yield threshold are replaced with lower yield ones from the initial population, resulting in enhanced computational speed and accuracy compared to other Monte Carlo-based methods. Simulation results for a two-stage class-AB Op-Amp in 180 nm CMOS technology show a yield of 99.72%, highlighting the method's effectiveness in achieving high speed and accuracy with a single evolutionary algorithm.

In this paper, a CMOS Operational Amplifier (op-amp) for applications requiring a bandwidth several hundreds of MHz will be designed and optimized. The op-amp is two-stage and compensated by current buffer and a Miller capacitor. In order to reduce the occupied silicon area, the compensation capacitor has been replaced with a capacitance transistor (MOSCAP). The most important issue in designing compensation networks for Amplifiers and particularly Operational Amplifiers is the calculation and selection of the optimal size for the circuit elements. After selecting op-amps designated by the user, the size of the circuit elements including transistors of the op-amps, along with the size of MOSCAPs, is determined by optimization algorithm, and the bandwidth, DC gain, power consumption and chip area will be optimized with this algorithm. Using the proposed technique, analytical relationship from the optimized solutions can be obtained. The obtained relationship indicates what is the best trade-off between phase margin, power and unity gain bandwidth which helps to achieve the desirable properties. A two-stage Amplifier based on CBMC techniques has been designed by a commercial 0. 18-µ m CMOS process. When driving a 1-pF capacitive load, the CBMC Amplifier acheives over 70-dB dc gain, 680-MHz gain-bandwidth product (GBW), 65o phase margin, and 350-V/µ s average slew rate, while it consumes only 900-µ W at a 1. 8-V supply. Nearly 34% improvement in bandwidth is obtained while the compensation capacitor size can be reduced to 1/3 of its original size.

A novel low-voltage two-stage Operational Amplifier employing resistive biasing is presented. This Amplifier implements neutralization and correction common mode stability in second stage while employs capacitive dc level shifter and coupling between two stages. The structure reduces the power consumption and increases output voltage swing. The compensation is performed by simple miller method. For each stage an independent commonmode feedback circuits has been used. Simulation results show that power consumption is 2.1 mW at 1 V supply. The dc gain of the Amplifier is about 70 dB while its output swing is as high as around 1.2 V.

This paper presents a Transimpedance Amplifier (TIA) for high sensitivity Near Infrared Spectroscopy (NIRS). The proposed TIA is based on the Regulated Cascode (RGC) structure with an extra transistor employed to implement additional feed-forward path and achieve higher gain values. The extra transistor senses a partially amplified input signal, available in the conventional circuit, and conveys an additional ac current into the load, which provides a higher gain. In addition, a bandwidth extension method is introduced using a capacitor and resistor, which can improve Amplifier’s bandwidth by 40%. The proposed TIA is designed in 0.18µm CMOS technology and achieves a transimpedance gain of 101.9dB with a -3dB bandwidth of 91.2 MHz considering 2pF of photodiode capacitance at the TIA input. The input referred noise is 4.4pA/√Hz while dissipating 151µW power.